Research and Professional Interests
I studied Computer Science at Saarland University, Germany, where I finished my Master's Degree (Diplom-Informatiker) in 1999. My master thesis was on highly parallel programming and database servers. From 1999, I was affiliated with the Institute for Computer Architecture at Saarland University as a PhD student and teaching assistant. In 2002, I completed my doctoral thesis on Formal Verification of Floating Point Units.
I have a background in software development for Enterprise Ressource Management Systems (ERM); I did frontend development under Windows, as well as backend database design, SQL programming, stored procedures, etc., on Informix and Oracle database systems.
In 1999 and 2000 I was working as an independent IT consultant for a large German telco, implementing a high-availability database cluster based on Sun E10K Solaris servers running Oracle databases in a SAP environment. I was working on automatic failover scenarios, automatic mirroring of the transactional database into a data-warehouse, backup, and disaster recovery.
I joined the IBM Research and Development lab in Böblingen, Germany, in 2002. I worked as a Logic Design engineer for the Floating Point Units of the Cell and Power6 processors. In 2004 I started to work on cache designs for System z mainframes, becoming the unit lead for the 2nd level cache unit in 2005. In 2007 I relocated to IBM Poughkeepsie, NY, to work as the unit lead for the L1 Cache. I moved back to Germany in 2010, where I was responsible for the development of all the private cache units of System z CPUs, as well as for future enhancements of the System z architecture. I was the lead engineer for the definition and implementation of the System z Tranactional Memory Facility. I work closely with software teams from hypervisors, operating systems (z/OS and z/Linux), compiler teams, and middleware, to co-optimize System z hardware and software.
In 2012 I moved back to Poughkeepsie. My current role is Chief Engineer for FPGA-based accelerator projects and other acceleration technologies. I also continue my responsibilities in CPU design.